SystemVerilog Trending
Trending SystemVerilog repos on GitHub · last 7 days
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
verilator
Verilator open-source SystemVerilog simulator and lint system
opentitan
OpenTitan: Open source silicon root of trust
tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
axi_mem_if
Simple single-port AXI memory interface
fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
i3c-core
register_interface
Generic Register Interface (contains various adapters)
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
sargantana
opentitan
OpenTitan: Open source silicon root of trust
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
verilator
Verilator open-source SystemVerilog simulator and lint system
axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
i3c-core
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
sargantana
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
opentitan
OpenTitan: Open source silicon root of trust
verilator
Verilator open-source SystemVerilog simulator and lint system
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
register_interface
Generic Register Interface (contains various adapters)
cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
axi_mem_if
Simple single-port AXI memory interface
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
common_cells
Common SystemVerilog components
sargantana
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
opentitan
OpenTitan: Open source silicon root of trust
verilator
Verilator open-source SystemVerilog simulator and lint system
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
opentitan
OpenTitan: Open source silicon root of trust
verilator
Verilator open-source SystemVerilog simulator and lint system
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
register_interface
Generic Register Interface (contains various adapters)
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
opentitan
OpenTitan: Open source silicon root of trust
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
verilator
Verilator open-source SystemVerilog simulator and lint system
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
Cores-VeeR-EL2
VeeR EL2 Core
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
i3c-core
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
verilator
Verilator open-source SystemVerilog simulator and lint system
common_cells
Common SystemVerilog components
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
Cores-VeeR-EL2
VeeR EL2 Core
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
i3c-core
register_interface
Generic Register Interface (contains various adapters)
axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
axi_mem_if
Simple single-port AXI memory interface