AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
📊 Project Info
- Language
- SystemVerilog
- Stars
- ⭐ 1,621
- Forks
- 360
- Ranking
- #10
- Collection
- Language
- Trending Date
- July 13, 2026
- Last Push
- 7/13/2026
🏷️ Topics
asicaxiaxi4axi4-litefpgahardwareipnetwork-on-chiprtlsystemverilog