Simple single-port AXI memory interface
📊 Project Info
- Language
- SystemVerilog
- Stars
- ⭐ 50
- Forks
- 29
- Ranking
- #10
- Collection
- Language
- Trending Date
- July 18, 2026
- Last Push
- 6/7/2024
🏷️ Topics
asicaxifpgasystemverilog-hdl
Simple single-port AXI memory interface