SystemVerilog Trending

adam-maj /

tiny-gpu

#5

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verilator /

verilator

#1

Verilator open-source SystemVerilog simulator and lint system

pulp-platform /

common_cells

#6

Common SystemVerilog components

lowRISC /

ibex

#4

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

openhwgroup /

cvfpu

#7

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

lowRISC /

opentitan

#3

OpenTitan: Open source silicon root of trust

chipsalliance /

caliptra-rtl

#2

HW Design Collateral for Caliptra RoT IP

adam-maj /

tiny-gpu

#1

A minimal GPU design in Verilog to learn how GPUs work from the ground up

lowRISC /

ibex

#5

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

lowRISC /

opentitan

#3

OpenTitan: Open source silicon root of trust

chipsalliance /

caliptra-rtl

#4

HW Design Collateral for Caliptra RoT IP

chipsalliance /

caliptra-ss

#2

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

adam-maj /

tiny-gpu

#1

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verilator /

verilator

#3

Verilator open-source SystemVerilog simulator and lint system

lowRISC /

opentitan

#2

OpenTitan: Open source silicon root of trust

adam-maj /

tiny-gpu

#1

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verilator /

verilator

#4

Verilator open-source SystemVerilog simulator and lint system

lowRISC /

opentitan

#2

OpenTitan: Open source silicon root of trust

openhwgroup /

cvfpu

#3

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

adam-maj /

tiny-gpu

#1

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verilator /

verilator

#4

Verilator open-source SystemVerilog simulator and lint system

lowRISC /

opentitan

#3

OpenTitan: Open source silicon root of trust

lowRISC /

ibex

#6

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

chipsalliance /

caliptra-rtl

#5

HW Design Collateral for Caliptra RoT IP

chipsalliance /

caliptra-ss

#2

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

adam-maj /

tiny-gpu

#4

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verilator /

verilator

#5

Verilator open-source SystemVerilog simulator and lint system

lowRISC /

opentitan

#2

OpenTitan: Open source silicon root of trust

lowRISC /

ibex

#6

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

chipsalliance /

caliptra-ss

#3

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

chipsalliance /

caliptra-rtl

#1

HW Design Collateral for Caliptra RoT IP

adam-maj /

tiny-gpu

#7

A minimal GPU design in Verilog to learn how GPUs work from the ground up

lowRISC /

opentitan

#1

OpenTitan: Open source silicon root of trust

verilator /

verilator

#5

Verilator open-source SystemVerilog simulator and lint system

lowRISC /

ibex

#8

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

openhwgroup /

cvfpu

#6

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

chipsalliance /

caliptra-ss

#4

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

chipsalliance /

caliptra-rtl

#3

HW Design Collateral for Caliptra RoT IP

pulp-platform /

common_cells

#2

Common SystemVerilog components