AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
📊 Project Info
- Language
- SystemVerilog
- Stars
- ⭐ 1,621
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- 360
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- #8
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- Trending Date
- July 12, 2026
- Last Push
- 7/8/2026
🏷️ Topics
asicaxiaxi4axi4-litefpgahardwareipnetwork-on-chiprtlsystemverilog