CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
📊 Project Info
- Language
- SystemVerilog
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- ⭐ 573
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- 537
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- #6
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- Trending Date
- July 12, 2026
- Last Push
- 7/9/2026
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