AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
📊 Project Info
- Language
- SystemVerilog
- Stars
- ⭐ 1,589
- Forks
- 353
- Ranking
- #6
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- Language
- Trending Date
- June 5, 2026
- Last Push
- 6/3/2026
🏷️ Topics
asicaxiaxi4axi4-litefpgahardwareipnetwork-on-chiprtlsystemverilog